Currently, many frequency multiplication circuits and systems rely at least in part on analog components and subsystems. Frequency multipliers are described in P. Horowitz & W. Hill, Digital Electronics (Cambridge University Press 1994) at pp. 886-887, which refers to them as non-linear circuits used when high stability signals are required at high frequencies above the range of good oscillators. Analog frequency multipliers unfortunately cannot be implemented as standard cell or gate array designs, because such designs can only implement digital electronic systems. Using analog features limits circuit design portability and adds to complexity and cost.
It is moreover desirable to engage in frequency multiplication without the involvement of higher frequency sources. It is further desirable to implement frequency multiplier systems able to accommodate variation in component characteristics and a modicum of defectiveness in system components.
It is additionally desirable to accomplish accurate frequency doubling and frequency multiplication independent of input clock duty cycle. In selected personal computer (PC) applications subject to power consumption reduction schemes, input clock duty cycles are variable due to irregular starting and stopping of clock operations. Many current frequency multiplication schemes are difficult to implement with irregular duty cycles of the input clock.
Complex fast-on, fast-off circuitry has been developed to accommodate analog frequency doubler and frequency synthesizer circuit requirements. Such complex circuitry is, however, expensive and problematic to operate and control.